Signal Integrity Optimization of PCB Layout When Using an External ESD Protection Device in Automotive SerDes Applications

In this paper authors present a method to improve the signal integrity of the SerDes automotive link APIX, to meet the signal integrity requirements even when using an external ESD protection. This was achieved by reduction of parasitic capacitance underneath the ESD protection device itself and the adjacent traces. 3D simulations in frequency domain up to 8 GHz, time domain reflectometry (TDR), and S-parameter measurements were used for validation of this method.