In-Memory Computation using Asymmetrical Schmitt Trigger SRAM cell

In-memory computation (IMC) addresses data processing directly within the memory itself. This approach eliminates much of the data transfer overhead, offering the potential for faster, more energy-efficient computation. This work looks into an Asymmetrical Schmitt Trigger based SRAM cell design for In-memory computation (IMC). The circuit is implemented using 45 nm technology, functions with an input frequency of 200 MHz, and uses a 0.8 V DC operating voltage. Performance metrics for the re-implemented asymmetrical Schmitt trigger SRAM cell recorded at 200 MHz include an output delay of 3.75 ns, an average power consumption of 3.12 µW and an energy per bit consumption of 3.58 fJ which shows 15.36% improvement in the energy per bit consumption at a cost of 52.44% decrease in SNM. The paper proposes an IMC based circuit for the implementation of all logic gates using Asymmetrical Schmitt Trigger SRAM cell.