Comprehensive Development and Testing of a 32-Bit Floating-Point ALU in Verilog

This project presents the design and implementation of a 32-bit Floating-Point Arithmetic Unit (FPAU) compliant with the IEEE-754 standard. As it is essential for precision in scientific computing, digital signal processing, and machine learning, the FPAU was developed using Verilog to ensure accurate and reliable arithmetic operations. Key methodologies included operand extraction and alignment, result normalization, rounding, and exception handling. These steps were critical to achieving compliance with IEEE-754 requirements. Simulations verified the unit’s ability to manage special cases like overflow, underflow, NaN, and infinity, confirming its accuracy and reliability. This project establishes a strong foundation for high-performance computing applications that require precise numerical calculations, highlighting the importance of standardized approaches in digital design.