Low Power SRAM Cell Design for Data Logging Application

The improved low-power 8-transistor (8T) SRAM cell discussed in this work is intended for data logging applications. This cell was designed using a transmission gate-grounded technique, which considerably lower power consumption compared to more traditional designs. The cell uses as little as 2.63 microwatts when using 180nm technology. The Cadence Virtuoso tool was used to simulate the design's performance. In addition to providing high-speed read and write operation, essential for data logging applications, the 8T configuration improves data retention stability and efficiency. Low-power applications that consider energy economy can benefit from this enhanced SRAM architecture.