Deep Insights of Negative Bias Temperature Instability (NBTI) Degradation

As the global semiconductor industry moving towards successive generations, the density of Integrated Circuit increased, therefore reliability issues became critically high, among them Negative Bias Temperature Instability is prominent one. NBTI degraded the PMOS transistor’s behavior when subjected to inverted gate voltage. The impact of NBTI can be referred to as threshold-voltage adjustment of PMOS, degradation in drain-source current, and reduction in speeds of device. An increase in temperature with negative gate stress is the primary introduction that degrades the Gate Oxide, which in turn causes all these adverse effects. Hence, stress analysis is required for any device before designing circuitry so that when circuits are drawn, high performance of the circuits is ensured. Out of many reliability problems affecting PMOS transistors at the nanoscale level, NBTI occupies center stage. This paper discusses stress-variation-dependent impact of NBTI for 22nm bulk CMOS inverter circuit over the period of 10 years.