FPGA Implementation of High-Speed Accelerators for CNN Architecture Using 3D Systolic Array Architecture

Convolution Neural Networks (CNNs) are pivotal in image processing. Prominent CNN models include SqueezeNet, MobileNet, Xception, VGG-16, and AlexNet. These models transform 2D data to 1D, emphasizing maximum intensity pixels for data flattening. Traditional systolic arrays are primarily linear and 2D; however, advancements in VLSI and packing technology have increased interest in 3D systolic architectures. This study proposes a 3D systolic architecture where input data is arranged on the X-Y plane, and filter coefficients are fed through the Z-X plane. The architecture utilizes multiplexers, multipliers, adders, 2:1 muxes, and delay registers. The model was developed using MATLAB and verified through HDL simulation on a Field-Programmable Gate-Array (FPGA). The 3D systolic architecture demonstrated an increase in area and operating frequency compared to conventional architectures, achieving a maximum frequency of 315 MHz and power dissipation below 5 W. The proposed 3D systolic architecture enhances the efficiency of CNN operations, offering a reusable subsystem for complex computations.