Light-Weight Low-Latency Reconfigurable CORDIC Architecture With a New Non-Power-of-2 Angle Set of Microrotations

Trigonometric functions are widely used in various scientific and engineering applications, including digital signal processing. This article proposes a low-complexity low-latency reconfigurable CORDIC (COordinate Rotation Digital Computer) algorithm that computes trigonometric functions, which is based on a novel angle set of microrotations. The CORDIC algorithm is an iterative algorithm that reduces the performance due to the high latency of computation. The proposed pipelined scale-free CORDIC algorithm computes the functions in only four iterations with an optimized angle set of microrotations with high accuracy. It can be configured in two modes with different trajectories 1) rotation-mode; and 2) vectoring-mode for circular and hyperbolic trajectories. On-board FPGA implementation of the proposed architecture consumes 34.95% less register, 48.12% less occupied slices, 19.06% less LUTs, 66.51% less slice-latency product (SLP), 59.29% less LUT-latency product (LLP), and 71.23% less register-latency product (RLP) compared to the best existing state-of-the-art CORDIC architectures. Moreover, the latency of the proposed architecture is 72.34% less than the best of existing designs. Besides, the parasitic-extracted layout simulation results of the proposed design across different word lengths are reported in TSMC 65-nm CMOS technology for the validation of the proposed architecture.