98-dB SNDR Multi-Residue Two-Step Incremental ADC With Two-Capacitor SAR

This brief presents a novel multi-residue two-step incremental ADC (IADC) with a two-capacitor SAR. It introduces the multi-residue sampling (MRS) technique to enhance Signal-to-Quantization-Noise Ratio (SQNR) and to minimize the thermal noise penalty commonly occurring in high-resolution IADCs. The multi-residue incremental ADC (MRIADC) was designed in a $0.18~\mu $ m CMOS process. It achieves an SNDR of 98 dB over a 2.4 kHz signal band. The power consumption is $78.76~\mu $ W from a 1.8 V supply voltage which gives Schreier Figure of Merit of 172.9 dB.