Memory Technologies for Crossbar Array Design: A Comparative Evaluation of Their Impact on DNN Accuracy

In-memory computing (IMC) using synaptic crossbar arrays offers a promising pathway toward energy-efficient deep neural network (DNN) accelerators. The potential of IMC is accentuated by virtue of IMC-compatible CMOS and non-volatile memory technologies, which offer various appealing features. However, each technology suffers from its own issues, which along with the crossbar non-idealities, significantly impair the DNN accuracy, especially in scaled technologies. In this context, a comprehensive cross-layer optimization to address the hardware non-idealities, coupled with a comparative evaluation of optimized technologies, remains largely unexplored. To address this need, we conduct a design space exploration and comparative evaluation of four prominent technologies—8T SRAM, ferroelectric transistors (FeFETs), resistive RAM (ReRAM), and spin-orbit torque magnetic RAM (SOT-MRAM) – at the 7nm node. We focus on the computational robustness in crossbar arrays and the influence of the technologies on DNN inference accuracy. We conduct IMC-driven optimization of each technology, accounting for both device- and circuit-level non-idealities. Using a cross-layer simulation framework that integrates physical models of synaptic devices and interconnects, we compare the inference accuracy of these technologies. Further, we throw light on the unique device attributes and device-circuit interactions that impact the DNN accuracy. Following this, we analyze the response of each technology to array size, bit-slice, and dataset/network complexity and how such design knob impact DNN accuracy. Our results for ResNet-20 with CIFAR-10 show that optimized FeFETs, due to their compact bit-cell layout and high distinguishability, lead to the highest accuracy, especially for large arrays. For more complex datasets (such as ResNet-50 with CIFAR-100) and larger bit-slices, ReRAM achieves performance comparable to that of FeFET. Lastly, we evaluate Partial Wordline Activation (PWA) and propose custom ADC reference levels as non-ideality-mitigating solutions and compare the response of each technology to these techniques.