Voltage Balancing and Energy Sorting of 17-Level Z Packed U-Cell MMC Using Real-Time Simulation

Modular Multilevel Converter (MMC) is a promising topology for medium-/high voltage applications due to its several features, mainly scalability, modularity, and reduced harmonics content. Yet, this complex topology faces several challenges in validating and verifying proposed control and modulation techniques due to its complex structure and difficulty in having a real prototype. Therefore, Real-Time (RT) simulation is an excellent alternative for verifying the operation of a MMC and its control while avoiding high-cost corrective methods. However, due to the excessive number of non-linear devices in MMC, which create additional computation burden, RT implementation of MMC becomes challenging as well. In this paper, a FPGA-based RT simulation is adopted for the implementation of a 17L-MMC based on Z Packed U-Cell Converter for its submodule, to verify the performance of voltage balancing and energy sorting algorithms, while obtaining efficient and accurate waveforms results.