FPGA-Based Hardware Implementation of Blue-Noise Stacked Error Diffusion Multitoning

Blue-noise stacked error diffusion (BSED) is a high-quality multi-level halftoning (multitoning) algorithm based on the blue-noise dithering model. This algorithm transforms a multitoning task into multiple error diffusion halftoning tasks, each producing a sub-halftone with inter-layer dependencies. These sub-halftones are stacked together to form the final visually pleasing multitone with blue-noise characteristics. In this research, the significant potential for parallelizing this multitoning algorithm inspires the design of a novel parallel raster image processor (NPRIP) for highly efficient execution, capable of producing an output pixel every six clock cycles at a clock frequency of 200 MHz. A hardware prototype based on the Xilinx Zynq SoC implements our raster image processor design on the FPGA within the SoC. The prototype is also capable of a conventional software implementation of the BSED algorithm running on the ARM CPU within the SoC. Output images from the prototype are successfully validated in both the spatial and frequency domains. Benchmark results demonstrate a consistent speedup exceeding $30\times $ with FPGA co-processing compared to conventional sequential execution on the ARM CPU, reaching a maximum processing speed of 3.963 megapixels per second.