FPGA Implementation of Sparse Matrix Vector Multiplication with Small-Scale Matrix Element Router

Sparse Matrix Vector multiplication (SpMV) is a fundamental operation in various computational science applications, characterized by a significant degree of inherent parallelism. Recent FPGA-based SpMV accelerators employ routing architectures such as crossbar switch or 2D-mesh network-on-Chip (NoC) to efficiently map matrix non-zero elements to their corresponding vector elements. The scale of these routing archi-tectures, however, serves as a key constraint on the attainable parallelism in FPGA-based SpMV accelerators. In this paper, we describe two approaches aimed at reducing the size of NoCs to exploit greater parallelism while suppressing the increase of hardware resource usage. In a previous work, each node in NoCs equipped multiple elastic buffers to prevent routing stalls, which was the main factor to increased resource usage. Our first approach replaces the elastic buffers to simple data registers to minimize the circuit size, while the second approach introduces ping-pong buffering to improve routing performance. Experimental results show that our approaches achieve 1.3 × to 1.7 ×throughput improvement over the previous work with less increase of resource usage.