A 59.2–83.3 GHz CMOS LNA With 18.1 dB Gain and 5.1 dB NF Using Gate-Drain Transformer

An E-band low-noise amplifier (LNA) is proposed for 6G applications. It employs three cascode amplifier stages, each utilizing a gate-drain transformer as the load. To extend the gain bandwidth, the pole tuning mechanism using the gate-drain transformer in the cascode amplifier is analyzed. A broad bandwidth with good gain flatness can be obtained by properly distributing the peaks of each stage amplifier. To further improve gain and optimize noise, an inductor is introduced to connect the common-source (CS) transistor and the common-gate (CG) transistor, which can counteract the adverse effects of parasitic capacitances. Fabricated in a 40-nm CMOS process, the proposed LNA occupies an area of 0.258 mm2 with all the pads. A maximum gain of 18.1 dB is attained with a 3-dB bandwidth across 59.2-83.3 GHz. The noise figure (NF) ranges from 5.1 to 8.1 dB. The input 1-dB compression point (IP1dB) is −14.5 dBm at 76 GHz. Furthermore, the LNA exhibits a DC power consumption of 26 mW with a supply voltage of 1.3 V.