A 12-bit 2-GS/s Pipeline ADC in 28-nm CMOS With Linear-Error Self-Calibration

This article discusses a 12-bit 2-GS/s pipeline analog-to-digital converter (ADC). A self-calibration technique is employed to correct linear errors due to capacitor mismatches and interstage gain errors (IGEs). To counteract the effects of power supply and temperature variations, the first three stages of the ADC are equipped with least-mean-squares (LMS) IGE background calibrations, enhanced by the injection of a 1-bit dither into these stages. The computational engines designed for background calibration were reused for self-calibration, simplifying the overall design. An improved integrated input buffer drives the ADC, achieving a bandwidth of approximately 6.3 GHz, which is essential for high-speed data acquisition and processing. Moreover, a low-power operational transconductance amplifier (OTA) and reference buffer, both operating on a 1.0-V supply, are implemented to minimize the chip’s power consumption. The 12-bit pipeline prototype ADC, fabricated using a 28-nm CMOS process, operates at 2-GS/s with a 1.0-Vpp input signal. It delivers a signal-to-noise-and-distortion ratio (SNDR) of 58.92 dB and a spurious-free dynamic range (SFDR) of 82.23 dB. The ADC core consumes only 180 mW, resulting in a Schreier figure of merits (FoMs) of 156.4 dB.