High-Performance Multipliers and Adder Designs in Digital Filters

Very Large-Scale Integration (VLSI) industries demand efficient multiplier designs for Digital Signal Processors. Research on multipliers has taken different paths to improve the efficiency of a multiplier in various parameters. This paper presents new efficient 8*8 multiplier designs namely the Weinberger Multiplier (Weinberger Adder-based Multiplier) and Composite Multiplier (Weinberger and Full Adder-based Multiplier). This paper also presents their implementation in a 5th-order transpose form FIR filter. Using 32nm technology in Cadence Virtuoso, the power, area, and delay values of the multipliers are presented. Furthermore, CMOS and GDI techniques are adopted to design multipliers at the transistor level. These two techniques have their advantages and drawbacks. CMOS technique is proven to be the best technique to adopt when the average power of the circuit is of primary concern but has circuit area and delay issues. The GDI technique is the best choice to improve efficiency in terms of area and delay but has the drawback of full swing at the output. To address the drawbacks of CMOS and GDI techniques and improve multipliers' efficiency in terms of power, area, and delay, intermixing the two techniques is adopted as the best choice for multipliers and filter designs. CMOS+GDI based Weinberger multiplier is 32.4%, 18.94%, and 30% efficient in transistor count, maximum power, and delay, respectively, compared to CMOS. CMOS+GDI based Composite multiplier is 65.2%, 43.1 %, and 91.22% efficient in transistor count, maximum power, and delay, respectively, compared to CMOS.