Reliability Analysis and Evaluation of PLC's Functional Diagrams

In industrial electronic systems, programmable logic controllers, or PLCs, find widespread application. Reliability becomes a key difficulty in safety-sensitive applications as system complexity increases. This paper presents a prescribed modeling and validation approach of the functional blocks in PLC's logic diagrams, and a logic specification system formalizes the functional block diagrams. We take up the subject of equivalency checking, which arises often when comparing design implementations with varying performance restrictions. We provide a novel approach to show the equivalency in a higher-order logic theorem proving system by utilizing a potent co-induction proof strategy via simulation. We provide a real-world example from industrial environment with essential scenarios to verify the efficacy of our technique. Our approach's completeness and soundness are supported.