Using Simulated Annealing for Application Mapping onto Network on Chip

The concept of Network on Chip (NoC) emerges as a new idea in System on Chip (SoC) interconnections, providing better integration of complex components. However, as a relatively new technology, it requires significant research efforts, particularly to streamline and simplify the design phases. The placement stage plays a crucial role in the network-on-chip design process. Ineffective mapping of application software components can significantly harm the overall performance of the end system. There is therefore a compelling need to improve the tools that automate this critical step. The main objective of this study is to create a new technique for placing applications on NoC architecture with the aim of minimizing communication costs. This innovative solution uses optimization algorithms, in particular simulated annealing