A Modulo Sampling Hardware Prototype and Reconstruction Algorithms Evaluation

Analog-to-digital converters (ADCs) play a vital important role in any device by digitally manipulating analog signals. Given that the amplitude of the signal exceeds the dynamic range (DR) of the ADCs, clipping occurs and the quality of the digitized signal degrades significantly. In this study, a joint modulo sampling hardware and processing prototype was developed which improves the ADCs’ DR by folding the signal before sampling. Both the detailed design of the hardware and the recovery results of various state-of-the-art processing algorithms including our proposed unlimited sampling line spectral estimation (USLSE) are presented. Additionally, key issues that arise during implementation are also addressed. With ADC thresholds of ±1 V and a sampling rate of 200 kHz, for the superposition of two sinusoids with amplitudes being 0.5 and 3 V, the USLSE algorithm recovers the signal with frequencies being 1 and 7 kHz, and the LP algorithm recovers the signal with frequencies being 1 and 8 kHz. For a baseband square-root raised-cosine shaped BPSK signal with the amplitude being 5.5 V sampled at 100 kHz, USLSE recovers the signal with a bandwidth of 1.83 kHz, and LP achieves recovery at 2.44 kHz.