A Ping-Pong Charge-Sharing Locking PLL With Implicit Reference Doubling and Simultaneous Frequency/Duty-Cycle Calibrations

We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator’s LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effectively achieving an implicit $2\times $ reference frequency multiplication. The design includes a simultaneous frequency-tracking loop (FTL) and duty-cycle calibration (DCC) loop for robust PVT tracking, employing an ultralow-power bang-bang phase-detector (BB-PD). A class-F3 oscillator along with its third harmonic extractor generate the ~27 GHz output. Implemented in 28 nm CMOS, the PP-CSL PLL demonstrates a threefold increase in injection strength compared to the conventional CSL PLLs, while resolving the load-modulation issue and improving the reference spur by ~15 dB. It achieves an ultralow rms jitter of 42 fs with a power consumption of only 14 mW, resulting in an outstanding jitter-normalized figure of merit ( $\rm FoM_{{\mathrm { jitter}}{-}N}$ ) of −276.6 dB.