Low Power Design of Pipelined Simon Cipher

Securing the data which is being transmitted between the devices is vitally important. With the improvements in technology security of the data is also becoming more essential each day. The devices with constrained environments are known as LRD’s (Low Resource Devices). The ciphers that are used to provide security for these devices where the available resources are limited by balancing the security with available resources are known as lightweight ciphers. In this paper, we have proposed a round function and pipelined architectures of one round and multiple rounds per stage using the proposed round function for Simon32/64. The ASIC implementation of the proposed architectures has been simulated and synthesized using the Cadence Genus Synthesis tool. The pipelined architectures of one and multiple rounds per stage using the existing round function and the proposed round function has been implemented and compared the results which shows that the pipelined architectures using the proposed round functions outperform the existing one by providing better results in terms of power reduction by 15%, throughput increment by 13% and area reduction by 13%.