Low power Energy efficient Dynamic Latched Comparator

A systematic study on various double tail dynamic comparator topologies is done for efficient portable ADC devices as comparator is the heart of ADC. In this paper, a new architecture that efficiently manages the power-delay trade off with the modified latch stage is proposed. The proposed method is designed and simulated in Cadence Virtuoso Analog Design Environment using 90nm CMOS technology. The proposed architecture offers a average power of 4.9uW, delay of 144ps, energy of 2.6fJ and power delay product of 0.705fWs. There is 68.3% reduction in the PDP when compared to conventional architecture.