Design and Implementation of Signed Radix-8 Booth Encoded Multiplier Using 5-3 Compressor

The Booth Algorithm provides an effective method in order to multiply signed binary numbers. The integration of radix Booth multiplication with compressors has revolutionized the industry, particularly in high-performance computing and digital signal processing units (DSP employed in digital systems. To ensure that enable quicker and more efficient processing, high-performance multipliers are essential components of FPGA’s and GPU’s. This work displays the conception and execution of a Radix-8 booth-encoded multiplier that uses a 5:3 compressor to accomplish signed multiplication. The aim is to enhance the delay but with the expense of increased area usage. Using radix-4 encoding, the Booth algorithm, which is highly recognized for its efficiency in signed multiplications, usually lowers partial products to n/2. By using radix-8 Booth encoding, this suggested method improves the procedure also minimises the total count of partial products to n/3. The radix-8 booth-encoded multiplier exhibits significant increases in speed when tested with other traditional multipliers, highlighting its potential in high-performance computing applications. In addition to this reduction, a 5:3 compressor is used, which drastically lowers latency and speeds up the resulting circuits.