FPGA-based Sentimental analysis on English words using Decision Tree Algorithm

This paper presents a new method for building a trained classifier integrated circuit from a completely automated dataset. The dataset is constructed using a 5-bit binary number, with 32 words assigned to each value, 21 of which are positive and 11 of which are negative. To classify them into positive or negative words, a machine-learning decision tree algorithm is utilized and real-time implemented using FPGA. For the considered data set, the values of entropy, the root node, and branch nodes are evaluated and the flow of the decision tree is derived to develop the Verilog code using the behavioral model. The developed Verilog HDL code is verified using the Xilinx Vivado Tool for the proposed design. The IC layout for the proposed design is designed using the cadence software with 90nm technology. The INCISIVE tool is used for the front-end part of the design. GENUS and INNOVUS tools are used in the back-end part of the design. The proposed method is analyzed for the parameters of power, area, and speed.