Low-Power High-Speed CNN Accelerator with Matrix Reodering Techniques for Small Footprint Memory Access

In the evolution of artificial intelligence (AI), large - scale data volumes are needed to best represent the information. This dataset is expressed by a matrix or tensor. When data volumes increase, the operational throughput of data processing increases, exponentially. However, this is not acceptable for computational devices, such as mobile devices, that are expected to low power consumption and high-performance. As the demands for embedded chip devices in AI software have increased, low-power and high-performance modules for AI software are needed to ensure efficient matrix or tensor data processing. Commonly, as performance enhances, power consumption also increases. In this point, a new matrix operation system is essential to ensure high performance and low-power consumption for efficient matrix data processing. In the matrix operation property, large amounts of computational operation can be reduced and sped up through parallelized data processing. In this paper, to determine the advantages of parallelized matrix operation in terms of performance and power consumption, hardware (ALU and memory) module chip equipped with a parallel operation structure and algorithm is designed to reduce data volumes and operational load. By implementing this module by Verilog, with a multicore processor, the processing speed and power consumption are able to compare with the existing sequential processing method of a single-core structure processor [1] [2]. We conducted an experiment to check the operation and performance of a parallelized module chip. The data are stored in memory to compression form through CNN algorithm software, and this is useful in the operation of the matrix arithmetic. This matrix arithmetic operation load is also reduced in support of the CNN algorithm software. The experimental results most likely confirm that the designed quad-core processor embedded CNN algorithm increased its speed to n*log n scale time complexity and that the memory usage rate, memory access footprint, and power consumption remarkably decreased.