The Impact of Process Steps on Nearly Ideal Subthreshold Slope in 300-mm Compatible InGaZnO TFTs

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) $\sim ~60$ mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T =4 K - 300 K) and multi-frequency (f =1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.

I. Introduction

The ultra-low off-current (I A/m) [1] and back-of-end-line (BEOL) process compatibility [2] of amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) has made IGZO transistors highly attractive for a plethora of applications, ranging from display technology [3], [4] to capacitorless 2T0C DRAM [1], [5], [6], 4F² DRAM [7], compute-in-memory [8], [9], and monolithic 3D integration [10]. In memory applications, the retention performance of DRAM cells is mainly determined by the I_off of write transistors utilizing IGZO channels [5], [6], [7], which is intrinsically linked to the subthreshold slope (SS) [11].