Design and Implementation of Novel Buffer-less NoC Router

In large tiled chip multiprocessors (TCMP), the connectivity between different processors is through Network on Chip (NoC). In NoC, NoC router plays a very important role. The two different types of routers are Buffered and Bufferless NoC routers. A bufferless NoC router is a viable solution due to its modest router architecture, hardware effectiveness and energy. Because several subnetworks are linked by an additional link amid two related routers, DeC allows a challenging flit in one subnetwork to be transmitted to other subnetwork rather than being deflected. NoC is defined by performance metrics such as latency, deflection rate, throughput, and power, all of which are dependent on the underlying network architecture. In this paper, a novel method such as Deflection Containment Path Distance Analyzer (DeC-PDA) Bufferless NoC router is proposed to solve the problem of extreme deflection during flit transmission. The results show that the area consumption is less compared to buffered routers.