A Testability Improvement Method of Combinational Circuits Based on the SDC Conditions

The testability of circuit decreases with the rapid increase of integration and complexity of modern chips. The synthesis technique for testability is important for the design of testable circuit, which reduces the test cost and achieves the high fault coverage. This work improves the testability of combinational circuits leveraging the Satisfiability Don't Care (SDC) conditions. The SDC condition refers the case that some input combinations of a circuit block can never occur because of the correlation between some input signals. The redundancy exists if the SDC condition is satisfied. In the proposed method, the adjacent-level SDC conditions and the cross-level SDC conditions are identified, and the related circuit blocks are simplified to improve the circuit testability. The Sandia Controllability and Observability Analysis Program (SCOAP) measures of benchmark circuits decrease if the proposed method is applied to the corresponding improved circuits. However, the reduction of the SCOAP measures is limited because the SDC conditions are rare in most of the benchmark circuits. To further reduce the SCOAP measures, the Observability Don't Care (ODC) condition introduced SDC blocks in the benchmark circuits are identified. The ODC condition refers the case that connection of a signal wire does not affect the circuit's logic function. More redundant blocks are found and simplified by utilizing the ODC introduced SDC blocks in the benchmark circuits. The Evaluation results show that average decrease of CC0 and CC1 is 14%, and the average decrease of CO is 15.3%. Additionally, it is observed that the proposed method is more effective for the larger scale circuits.