Large Language Model Driven Logic Locking: A Generative Approach to Secure IC Design

Logic locking has emerged as a critical solution for secure integrated circuit design, protecting hardware intellectual property from reverse engineering, piracy, and unauthorized access. Recently, large language models (LLMs) and generative model-based logic locking emerged to automate the obfuscation process and enhance security in hardware designs. Prior research on generative pre-trained transformer-based logic obfuscation faces challenges with prompt retention and circuit connectivity in larger designs. This article presents an iterative prompt-based framework that refines the generated netlist over multiple iterations to generate an obfuscated design. Experimental evaluation demonstrates the framework’s effectiveness in generating an obfuscated netlist. The article discusses the research challenges of LLM-based logic locking and outlines future work to develop a scalable and efficient framework for secure hardware designs.