Design and Implementation of RDMA Multi-Queue Data Shared Cache Circuit

With the rapid development of technologies such as cloud computing, big data, and the Internet of Things, RDMA (Remote Direct Memory Access) technology has been widely applied due to its high bandwidth and low latency characteristics. However, the use of RDMA technology faces challenges such as significant consumption of multi-queue data cache resources and the fixed cache size limiting RDMA communication bandwidth and latency performance‘!’, To address the issue of high storage resource consumption and long data management and scheduling times in RDMA multi-queue management, this paper designs and implements an RDMA multi-queue shared cache management mechanism. The shared cache is divided into blocks, and a free pointer FIFO is used to efficiently allocate and reclaim data blocks. A linked queue is used to implement isolation and dynamic allocation between multiple queues. Meanwhile, both the linked queue and shared cache reuse the same free pointer FIFO for management, reducing the complexity of the management circuitry and resource overhead. The multi-queue shared cache mechanism designed in this paper is integrated into the RDMA NIC system, implemented on the VCUl18 platform. The results show that the system occupies 36% of the on-board storage resources, operates at a clock frequency of up to 250 MHz, and supports RDMA Read at 80Gbps and RDMA Write at 90Gbps transmission rates, with a latency as low as 3 μs.