MTJ/CMOS-Based CLB Design for Low-Power and CPA-Resistant Secure Nonvolatile FPGA

Modern applications such as the Internet of Things (IoT) devices, AI, and automotive applications widely use field-programmable gate arrays (FPGAs). However, many of these applications have limited power resources. Also, the existing FPGAs are vulnerable to side-channel attacks (SCAs) such as correlation-based power analysis (CPA) attacks. Therefore, designing low-power, CPA-resistant, and secure-by-design FPGA is required. In this article, two low-power and CPA-resistant hybrid CMOS/magnetic tunnel junction (MTJ) logic-in-memory-based configurable logic blocks (CLBs) have been proposed and compared to a state-of-the-art counterpart. The first proposed design is single output, and the second one is multioutput. The simulation results show that compared to the state-of-the-art secure CLB counterpart [secured CLB (sCLB) by Zooker et al. (2020)], the proposed CLB designs have 42% and 33% lower delay, 85% and 18% lower power consumption, and 86% and 63% fewer equivalent transistors. To implement one round of the PRESENT algorithm, the first and second designs have 85% and 77% fewer transistors, 42% and 33% lower delay, and 86% and 50% lower power consumption compared to their silicon-proven secure counterpart. Also, to implement convolution layers of binarized neural network (BNN), compared to this counterpart, the first and second proposed designs have 85% and 90% fewer equivalent transistors, 42% and 33% lower delay, and 86% and 79% lower power consumption. Also, the resiliency of the proposed designs against power analysis attacks has been investigated by exhaustive simulations and performing CPA attacks on PRESENT and Advanced Encryption Standard (AES) SBOX. Also, this resiliency has been investigated for different tunnel magnetoresistance ratios (TMRs) and supply voltages.