Area-Optimized and Low Power Ripple Carry Adder

VLSI design is the process of integrating millions or billions of transistors onto a single chip for use in electronic devices ranging from simple hand-held devices to supercomputers. Modern devices demand low power, high performance, low cost and areaefficient chips. The cost and area can be reduced by scaling MOSFETs. Switching of logic states and leakage currents is the main reason for power dissipation. Designing high-performance and low-power-consuming systems becomes difficult due to the increasing complexity and density of the chip. A low power Ripple Carry Adder is proposed in this work. The carry logic of conventional full adder is approximated to perform area and power-efficient addition and this modified full adder block is used in the ripple carry adder to reduce power consumption. The proposed 4-bit ripple carry adder results in power saving of 12.92% and a notable reduction in LUT utilization by 50%. The design metrics were implemented on Diligent Basys 3 FPGA Board, following the simulation in Xilinx Vivado v2023.2 software environment.