An Asymmetric Dynamic Comparator for Low-Offset, Low-Noise, and High-Speed Applications

An asymmetric preamplifier-based dynamic comparator is proposed for low-offset and high-speed applications. The design is implemented using an additional capacitor and five transistors. Initially, the capacitor stores the offset voltage which is later used to introduce asymmetricity in the preamplifier. The resultant comparator offers low latency and low input-referred noise. The comparator is designed and simulated in United Microelectronics Corporation (UMC) 65-nm CMOS technology using a 1.2-V power supply. It operates at a frequency of 1 GHz and consumes 44-fJ energy with a latency of 52 ps. The Monte-Carlo simulations are performed for 500 samples which results in a worst case offset of 3 mV. The proposed comparator reduces the offset by 10 times compared to the conventional design. Moreover, the proposed comparator achieves 0.48 mV (rms) input-referred noise without sacrificing energy.