Semiconductor Wafer Defect Recognition Based on Improved Coordinate Attention Mechanism

In the semiconductor wafer manufacturing process, it is necessary to inspect the electrical parameters and functions of the wafer to identify the defects in the chip manufacturing process. The inspection results are presented in the form of wafers; therefore, the accuracy of wafer defect recognition directly affects the chip yield. Traditional manual methods suffer from subjectivity, inefficiency, and diminished accuracy. With improvements in computing power, computer vision based on convolutional neural networks has demonstrated notable advantages in defect recognition. Nonetheless, with the development of Moore’s law and the continuous increase in wafer size, it continues to contend with challenges regarding the accurate identification of mixed, complex types of wafer defects and necessitates distinct training for each defect type, a process that is both laborious and time-intensive. In this study, we introduce a new deep learning model called the Deep Attention Pyramid Network (DAP-Net), which is based on depth-wise separable convolution and combines an improved coordinate attention mechanism with a multi-scale convolution structure to identify single and mixed types of wafer defects. Our model achieved an impressive recognition accuracy of 98.6% when evaluated on a mixed-type defect dataset (Mixed38WM), surpassing the performance of most previously reported deep learning models.