A Parallel Read-Write Circuit With Fast Amplitude-Adaptive Matching Scheme to Memristor Crossbar Array

Memristor crossbar array (MCA) is a computing-in-memory (CIM) module for computational acceleration. However, conventional read-write (R-W) circuits for MCA rely heavily on external components and have shortcoming in long writing times. To address these issues, we propose a parallel R-W circuit with a fast amplitude-adaptive matching (AAM) scheme. The fast AAM scheme is designed to accelerate time of writing memristors in MCA by adaptively adjusting the writing voltage to match an optimal amplitude. The architecture of parallel R-W circuit are outlined with the implementation of R-W processes. The design principles of parallel R-W unit, fast AAM unit, and associated control logic are described for analyzing their functions within the circuit. By integrating the parallel R-W circuit with MCA, a computing block is leveraged in a neural network for classification tasks. The experimental results demonstrate that the neural network with multiple computing blocks maintains high accuracy across various datasets (over 80%). Furthermore, the proposed AAM scheme achieves an average 54% reduction in writing time compared to that one without AAM scheme. Compared to the pulse-width scheme, the parallel R-W circuit exhibits an average 3.05× speedup in adjusting a 5×5 MCA, and the speedup efficiency is higher as the increases of MCA size.