Design and Analysis of Low Noise Figure High Gain CMOS Low Noise Amplifier for 5G Applications

This paper presents an ultra-wide band (UWB) low noise amplifier (LNA) with low voltage linearization. The three-stage cascade structure at the core of the proposed circuit is forward body biased to work with a low supply voltage. The second stage of the proposed topology makes use of the modified derivative superposition (MDS) technique to address the low linearity flaw of the cascade structure.The benefit of using the MDS technique on a cascade structure is that a UWB LNA can have good linearity and low supply voltage qualities. The structure has an 18.79 dBm IIP3 and is simulated in 28 nm CMOS UMC technology. It uses only 12.67 mW from a low supply voltage of 0.5 V. The proposed LNA achieves a return power loss of less than -13.7 dB, a noise figure of 1–4 dB, and gain above 25 dB.