Evaluation of Power Distribution Network Based on the Standard Deviation of Dynamic Voltage Noise for Multichip System

Advanced packaging is increasingly recognized as a cost-effective solution to enhance the performance of the single-chip/multichip system. However, due to the multiplication of the transistors in one chip, the dynamic voltage noise of the single chip and the coupling voltage noise of multiple chips has become more severe than ever before. The key to controlling the dynamic voltage noise of the chip is to design the power distribution network (PDN) of the single-chip/multichip system well. This article proposes a method, called integrated power noise (IPN), that can judge whether the PDN of the chip is well-designed during the early design stage. The standard deviation of the dynamic voltage noise of the single-chip/multichip system is precisely and efficiently calculated as a criterion for evaluating the quality of the PDN design, which leverages the Z-parameter of the PDN and the power spectral density (PSD) of the current consumption waveform. State-of-the-art methods and the IPN for assessing dynamic voltage noise in the single-chip/multichip system are compared. The IPN demonstrates better efficiency and accuracy in calculating the standard deviation of the dynamic voltage noise of the PDN for a single-chip/multichip system.