Precise Subclock Period Delay in Digital Radar Target Simulation

In the digital radar target simulation, the period of the digital signal processing clock determines the tiniest step in signal delay. The signal delay determines the range of the simulated target. Therefore, the step in signal delay corresponds to the range resolution of the target simulator. This article proposes three methods on how to increase signal delay resolution in the digital domain below the clock period. The improvement is from resolution in the range of tens of centimeters to several millimeters. The first technique optimizes the organization of the sample stream. The second is based on the deployment of the tapped delay line. And the third method utilizes precise phase shifting of the sampling clock. The proposed techniques can be combined to achieve the desired delay resolution. The methods are implemented and evaluated on a field-programmable gate array (FPGA)-based automotive radar target simulator (RTS) in the 80-GHz band.