FPGA-Based Implementation of Single-Cycle High-Throughput LDPC Encoder for 5G New Radio

This paper presents a novel architecture for a high-throughput encoder for quasi-cyclic low-density parity-check (QC-LDPC) codes. This low-complexity encoder is specifically tailored for the 5th Generation (5G) New Radio (NR) standard. To achieve high throughput, we employ an automated approach to design customized encoders for individual base graphs using a Verilog Code Generator (VeCoGen) that we developed in MATLAB. Our proposed architecture improves efficiency by rearranging the wire indices during the hardware design language (HDL) code generation stage itself, instead of performing shifting operations on the data carried by those wires on the fly. This eliminates the need for RAM (for storing base graph coefficients) and dedicated barrel shifters. The parity bits are computed in parallel, while maintaining optimal performance and gate count through effective exploitation of the base graph’s sparsity. Consequently, the encoder can be designed as a fully combinational circuit between the input and output registers, enabling the generation of the complete codeword within a single clock cycle. This results in exceptionally high throughput, optimal hardware utilization, and minimal number of XOR operations, making our approach highly effective for 5G NR applications.