8.5 A Command-Aware Hybrid LDO for Advanced HBM Interfaces with 150μA Quiescent Current and 20pF On-Chip Capacitor Achieving Sub-10mV Voltage Droop in 400ps Settling Time

With the advent of the generative AI era, high-bandwidth memory (HBM) has emerged as an irreplaceable solution that can provide ultra-high memory bandwidth (BW) of more than 1TB/s to AI processors. To enable such a high BW, HBM3E accommodates 16 channels (CHs) with two pseudo CHs (pCHs) each, and HBM4 increases them to 32 CHs to double the BW. Each pCH receives a dedicated differential write data strobe (WDQS) from the host. Then, the quadrature clocks (WDQS/2INS) at half frequency are passed to the WDQS buffer, which generates the output clocks, 5OUTxS (X = I, Q, IB, QB), to sample the DQ data in parallel (top left of Fig. 8.5.1). To ensure error-free sampling for all DQs, low jitter is necessary in the $S_{\text{OUT}X}\mathrm{s}$, but it is difficult to achieve due to the power-supply-induced jitter (PSIJ) issues of the WDQS buffer. A sudden toggle of WDQS/2IN in response to the command signal $(ACT_{\mathrm{C}\text{MD}})$ from the host causes a surge in the instantaneous load current $(l_{\mathrm{L}})$ of the WDQS buffer (e.g., edge time (TEDGE) < 100ps) [1] (top right of Fig. 8.5.1). This results in a significant voltage droop in the supply voltage $(V_{\mathrm{D}\mathrm{D}})$ and a substantial increase in PSIJ [2]. This problem is particularly severe when the $V_{\mathrm{D}\mathrm{D}}$ is unstable and noisy due to complex power grids and limited capacitor availability.