37.2 A 2-Dimensional mm-Scale Network-on-Textiles (kNOTs) for Wearable Computing with Direct Die-to-Yarn Integration of 0.6×2.15mm2 SoC and bySPI Chiplets

This paper proposes a scalable, 2-dimensional network-on-textiles (kNOT) comprised of systems-on-chip (SoCs) and “bySPI” networking chiplets that are jointly capable of supporting heterogeneous programming, multiple sensing modalities, and a distributed memory system. Emerging e-textiles must retain the flexibility and comfort of their host garment to be viable in wearable applications for healthcare, virtual reality, and sports [1]–[4]. Prior integration efforts have demonstrated textile computing by weaving flexible filament circuits [5]–[7], embroidering conductive yarns [8], and fabricating electronic fibers [9]–[10]. Still, these works suffer from a combination of bulky, rigid components, high cost, or 1-dimensionality (Fig. 37.2.1). To preserve the textile's look and feel, SoCs for fabric integration must also be highly miniaturized, feature minimal area-hungry IO interfaces, be easily programmable, and be fully integrable. The e-textile system in [11] integrated a health sensing chip onto a planar fashionable circuit board, yet the board (25×25mm²) is 40× larger than the chip itself. The System-in-Fiber from [12] is fully autonomous but has many IO pads, is limited to 1D networks, and requires an interposer (4.7×3.7mm²) that is 3.8× larger than the die. Most recently, a battery-less e-textile system in [13] integrates cm-scale harvesting tiles and an inductor onto a shirt, but it lacks an integrated SoC. Many wearable applications also demand substantial on-garment storage, yet large memories are unsuited for comfortable textile integration due to their sizable footprint. Our kNOT solution addresses this by replacing monolithic memory units with a distributed set of smaller memories. However, networking these chiplets via existing bus standards incurs significant area and power penalties [14]. Existing Body Area Networks highlight the potential of multi-chip solutions, but they lack seamless textile integration [15]–[17]. Hence, to truly realize a fabric computing system, we propose a board and interposer-free 2D kNOT built with the direct-die attachment of two miniaturized chiplets: 1) an SoC with an array of reconfigurable pads, fault-tolerant global bootup, SoC-to-SoC clock synchronization, and dynamic network configuration; and 2) a bySPI chiplet which is a COTS-compatible, reduced-wire enhancement of the bypass-SPI (bySPI) protocol [14] capable of connecting to any number of receivers (RXs) using three wires. The chiplets are directly interconnected to braided composite yarns, which are comprised of para-aramid structural yarns and insulated 25μm-diameter conductors [26]. For each pad, a yarn is embroidered into a cotton substrate and its insulation is selectively ablated using a laser. Solder paste is deposited, the chiplet is placed to align its pads with the yarns, and the solder is reflowed. The interconnections are then encapsulated to provide mechanical and environmental protection. This textile-chiplet interconnection approach is compatible with automated high-throughput 2.5D electronics manufacturing methods, enabling the production of textile-integrated systems at scale (Fig. 37.2.1).