36.1 A 32Gb/s 10.5Tb/s/mm 0.6pJ/b UCIe-Compliant Low-Latency Interface in 3nm Featuring Matched-Delay for Dynamic Clock Gating

Demand for chiplet integration using 2.5D or 3D packaging has surged due to the AI/MLdriven growth in computing performance. Universal Chiplet Interconnect Express (UCIe) has been developed to standardize chiplet interconnects, focusing on bandwidth density, energy efficiency, and latency. Dynamic clock gating is crucial for reducing power consumption, but transitioning from clock-gated to ungated modes introduces challenges due to the instantaneous current surge (Di/Dt), which can cause significant supply voltage droop. This droop leads to data sampling misalignment and bit errors. This paper presents a 32Gb/s, 64-lane UCIe module with a matched-delay architecture designed to address these challenges and ensure low power and low latency operation.