34.1 A 65fsrms-Jitter and -272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration

A digital PLL (DPLL) using a BBPD represents the optimal architecture for designing frequency synthesizers in a nanometer-scale CMOS technology because it minimizes reliance on analog circuits that require large headroom and numerous passive components. However, designing a fractional-N DPLL with low jitter, particularly at the sub-100fs level, is highly challenging due to the diverse quantization errors (Q-errors) that are inherent in digital circuits. To mitigate these Q-errors, various techniques have been proposed [1]–[5]. Recently, a common solution has involved using a digital-to-time converter (DTC) to eliminate the Q-error of the $\Delta\Sigma \mathrm{M}$ [6]–[13], which is the most dominant among various Q-errors. However, the DTC itself generates additional thermal noise that is proportional to the amount of delay [14], and this becomes another major source of in-band phase noise (PN). The DTC delay consists of a dynamic delay that is tunable to cancel the $\Delta \Sigma M$ Q-error and a static delay that is inevitably generated when producing the dynamic delay. To cover a wider range of the $\Delta\Sigma \mathrm{M}$ Q-error, the DTC must be designed with a larger dynamic delay range, and this also increases the static delay. A straightforward approach to reducing the thermal noise of the DTC is to use more power, but this inevitably degrades the overall jitter-power FoM $[\text{FoM}_{\text{iitter}}]$ of the DPLL. This dilemma underscores the need for a new design to cancel the $\Delta\Sigma M$ Q-error.