24.6 A Power- and Area-Efficient 4nm Self-Calibrated 12b/16GS/s Hierarchical Time-Interleaving ADC

Array processing systems for wideband communication and sensing applications are progressively using a growing number of analog/RF elements. These systems require multiple identical analog-to-digital converters (ADCs) in fine lithography systems-on-a-chip (SoCs) for digital processing. Thermal and area constraints lead to increasingly stringent requirements on the individual power consumption (hence efficiency), physical size (hence cost), of all the integrated functions, including the data converters. This paper introduces an interleaved 12b/16GS/s ADC, implemented in a 4nm FinFET process, which addresses power and area challenges by incorporating innovations at both architecture and circuit levels. The ADC consumes 570mW, including calibration, on-chip supply regulation, reference buffers etc., with a Schreier figure of merit (FoMs) of ~148dB at Nyquist and an area of 0.430mm². It achieves a small-signal (-30dBFS) noise spectral density of -155dBFS/Hz, non-harmonic spurs better than -68dBFS (for a -1dBFS input tone at 7.4GHz), and a high-frequency SFDR of ~58dBc (also -1dBFS input tone at 7.4GHz) limited by HD2 (-58dB) and HD3 (-64dB), advancing the state-of-the-art.