29.5 A 3nm 3.6GHz Dual-Port SRAM with Backend-RC Optimization and a Far-End Write-Assist Scheme

Dual-port (DP) SRAM offer simultaneous read and write operation with two asynchronous clocks, and can realize higher read and write bandwidth from two different clock frequency domains [1]–[5]. However, design complexity is higher than for a single-port (SP) SRAM, when considering worst-case operation. In addition, resistance degradation, caused by process scaling, becomes more severe in leading-edge technology nodes, we must consider resistance and capacitance (RC) impact in the circuit design. In this paper, we report a 20kb DP-SRAM in a 3nm process technology with $0.052\cup \mathrm{m}^{2}$ DP-SRAM cell. Increased design-technology co-optimization (DTCO) opportunities in the DP-SRAM cell and its peripheral circuitry enable the DP-SRAM macro to realize better area scaling compared to SP-SRAM. Although an array dual-rail design (ADR) with $\mathrm{v}_{\text{DI}}$ for the peripheral region and $\mathrm{v}_{\text{DDM}}$ for the cell array region is used to enhance energy efficiency, additional design considerations are required because we need to consider $\mathrm{V}_{\text{DD}} > \mathrm{V}_{\text{DDM}}$ and $\mathrm{V}_{\text{DDM}} < \mathrm{V}_{\text{DD}}$ conditions. To overcome these design challenges, we introduce a far-end write-assist scheme and an update to the wakeup scheme in the power management circuitry. Measurement results show a minimum operating voltage $(\mathrm{V}_{\mathrm{M}1\mathrm{N}})$ becomes 495mV at 95% yield at -40°C. We also observed 2.02, 2.64 and 3.6GHz operation at 0.7,0.8 and 1.0V at -40°C.