7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET

The growing demand for higher communication bandwidth between processors through wired interconnects in large-scale servers has been driving the need to increase the per-lane data rate beyond the current 112Gb/s. Recently demonstrated analog-to-digital converter (ADC)-based receiver (RX) prototypes with>100Gb/s data rate typically employ a parallel feed-forward equalizer (FFE) with a large number of taps, 1-tap decision feedback equalizer (DFE) [1]–[5], and maximum likelihood sequence estimator (MLSE) as option [6]–[8]. As the data rate grows exponentially, the pulse response length and the number of corresponding inter-symbol interference (lSl) cursors increase accordingly [5], [8]. As the length of the pulse response gets doubled, the FFE tap count also needs to be increased accordingly, which results in substantial area and power overhead. The DFE feedback loop timing closure also gets more stringent as Baudrate increases [9]. With an increased pulse amplitude modulation (PAM) order, the DFE and MLSE design complexity increases exponentially [6]–[8]. While $\mathrm{a} > 100\text{Gb}/\mathrm{s}$ PAM-4 transceiver (TRX) can effectively equalize smooth channels [2]–[5], ripples and notches in the frequency response of the channel can significantly degrade the equalization performance of the current PAM-4 TRX.