24.8 A 12GS/s 9b 16× Time-Interleaved SAR ADC in 16nm FinFET

Time-interleaved (TI) SAR ADC architecture is preferred in the low-to-moderate resolution space to achieve >GS/s speed for its excellent power and area efficiency [1]–[3], as well as to reduce design complexity, which may lead to fewer tape-outs and faster product development. High-speed and medium-resolution ADCs are used in applications like wireless communications and portable instrumentation. Emerging applications such as RF direct sampling in fully digital phased arrays require similarly high sample rates, but they also demand RF SNDR beyond 45dB. In [4]–[6], high-speed SAR ADCs with such SNDR were reported. Often, 3 or more supply domains are utilized and tailored for optimized analog performance, as in [4], [5], making integration into a larger transceiver system difficult. In this paper, we present a 12GS/s 16× TI SAR ADC that achieves 48.1dB SNDR at 5.3GHz input, consumes 160mW from integration-friendly 1.8V and 0.8V standard process supplies and occupies $0.25\text{mm}^{2}$ in 16nm FinFET.