A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS

The development of artificial intelligence and high-performance computing has fueled the demand for increased edge density and reduced bit error rate (BER) in die-to-die interfaces. One approach to improving the edge density is increasing the per-wire data rate [1]–[5]. Four-level pulse amplitude modulation (PAM-4) is adopted to double the data rate; however, the degraded SNR makes it challenging to achieve an extremely low BER [2]. Simultaneous bi-directional (SBD) signaling is another effective method to double the data rate, but it is vulnerable to echo and crosstalk. An echo cancellation (EC) circuit is presented in [6], but it consumes significant power, making it unsuitable for die-to-die interfaces. Ground shielding is inserted in [4] to reduce crosstalk, but it limits the edge density improvement. Another approach to improving the edge density is decreasing the data channel pitch. With the crosstalk cancellation (XTC) technique implemented, ground shielding can be removed to halve the pitch for a doubled density [7]–[8]. However, these conventional XTC techniques only cancel the far-end crosstalk (FEXT), which is insufficient for SBD signaling as the near-end crosstalk (NEXT) also impacts data receiving. This work presents a 64Gb/s/wire single-ended SBD transceiver with echo, NEXT, and FEXT cancellation for shield-less channels, achieving an edge density of 1 0.5Tb/s/mm/layer at less than 10–¹⁶ BER on a 3mm on-chip channel.