A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique

Recent advancements have broadened the use of capacitive sensors from traditional low-speed fields, such as measuring pressure [1] and humidity [2], to real-time applications like robotics and drones. E.g., high-performance MEMS motion-tracking devices feature a short measurement time of $31.25\mu\mathrm{s}$ [3]. These developments necessitate capacitance-to-digital converters (CDCs) with high resolution, good energy efficiency, and low latency. The zoom architecture, combining the merits of energy-efficient SAR with high-resolution $\Delta\Sigma\mathrm{M}$, draws rising attention [4]–[6]. Owing to the scaling friendliness and high efficiency, the VCO-based time-domain (TD) $\Delta\Sigma\mathrm{M}$ has been explored lately for the fine stage [7]–[9]. The VCO stage features intrinsic phase integration, thus obviating the need for power-hungry OTAs. The digitized phase output allows low-cost multi-bit quantization, largely reducing the required OSR and thereby enhancing both speed and power efficiency. Nevertheless, this architecture still faces two key challenges in achieving higher performance. 1) The reduced OSR exacerbates the sampling noise problem due to insufficient averaging. Although kT/C noise cancellation can alleviate this issue, it requires additional amplifications, bringing extra time and power $\mathbf{r}$ consumption [9], [10]. 2) Compensation techniques are essential for the stability of high-order loops. Feedforward compensation is favored owing to its better linearity and lower hardware cost. Yet, there still lacks an efficient feedforward method due to the VCO's intrinsically fused integrator and quantizer [11].