19.4 An 8.1-to-9.9GHz Single-Core Pseudo-Series-Resonance Oscillator Achieving -128.7dBc/Hz PN at 1MHz

As data-rate requirements in $5\mathrm{G}$-Advanced and future $6\mathrm{G}$ communications continue to rise, an RF oscillator with ultra-low phase noise (PN) is a prerequisite for ensuring higher-order modulation schemes and ever-higher throughput. Under the CMOS-limited supply voltage and power-dissipation constraints, the PN in conventional parallel-resonance (PR) LC-tank oscillators is primarily limited by the tank quality factor (Q). To continue the quest for ever-lower PN, $N$ oscillators can be coupled together for an effective PN reduction of $10\log(N)$ (Fig. 19.4.1, top-right) [1]. However, the practical implementation of multicore oscillators is hampered by 1) mismatches between the cores, which degrades the achievable PN and figure of merit $(\text{FoM})$, and 2) the area-intensive floorplan required when coupling many cores. Series-resonance (SR) LC oscillators have the potential to achieve ultra-low PN with a single-core configuration [2]–[4]. Nonetheless, several challenges arise when implementing this configuration in CMOS: 1) Realizing a cross-coupled oscillator core that provides current-controlled negative resistance is difficult in CMOS; although, it can be achieved in bipolar technologies with additional diodes (Fig. 19.4.1, bottom-left) to maintain the output voltage amplitude [3]; 2) four-stage inverter-based SR oscillators (Fig. 19.4.1, bottom-middle) require $4\times$ the power consumption and introduce additional noise from active devices to maintain the oscillation, as each series-LC tank provides a $90^{\circ}$ phase shift [4]. Both reported works burn over $300\text{mW}$.