19.10 A 4.6GHz ${63.3}\text{fs}_{\text{rms}}$ PLL-XO Co-Design Using a Self-Aligned Pulse-Injection Driver Achieving −255.2dB $\text{FoM}_{\mathrm{J}}$ Including the XO Power and Noise

With the advancements in low-noise-circuit techniques, phase-locked loops (PLLs) have been pushing their jitter figure of merits $(\text{FoM}_{\mathrm{J}})$ to −260 and −255dB for integer- and fractional-N modes, respectively. The in-band noise and power are improved with sub-sampling, over-sampling, and digital techniques [1]–[6], while advanced LC-oscillator methods [7]–[9] reduce their power and out-of-band noise, achieving under $50\text{fs}_{\text{rms}}$ integrated jitter with a few mW of power consumption. However, the power and noise optimizations historically overlook the full frequency-generation-and-synthesis chain, including the crystaloscillator (XO) driver, reference buffer, and the PLL.